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Nanopack Project
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Large Scale Integrating IP Project: Nano Packaging Technology for Interconnect and Heat Dissipation

 

One of the major limitations to continued performance increases in the semiconductor and power electronicshome2 industries is integration density and thermal management. Continued transistor downscaling is quickly reaching its limits forcing a new focus on heterogeneous integration and 3D packaging in order to further push performance and density. Improved thermal management and integration densities increase energy and manufacturing efficiency and component reliability. In NanoPack we develop new technologies and materials for low thermal resistance interfaces and electrical interconnects. Modeling and simulation techniques with world class supercomputers will be combined with the develop¬ment of experimental test structures to measure the performance of new interface technologies and validate design tools. Finally the technology will be demonstrated in high powerhome3 radio frequency switches, microprocessors and hybrid vehicle power electronics.

 

Three parallel approaches will be pursued to improve thermal and electrical performance: Enhancement of home4bulk conductivity of filled systems, reduction of bondline thickness, and optimization of nanoscale thermal and electrical contact surfaces. Nanopack fills several gaps reported by the ITRS roadmap and covers several ENIAC strategic research agenda focus topics in the heterogeneous integration area. The NanoPack consortium consists of 4 major industrial partners, 4 innovative SMEs, and 6 academic groups in total representing 8 European countries:

 

Thales Research home5and Technology, Paris, France (coordinator)
Berliner Nanotest and Design GmbH, Berlin, Germany
Budapest University of Technology and Economics, Budapest, Hungary
Catalan Institute of Nanotechnology, Bellaterra, Spain
Chalmers University of Technology, Gothenburg, Sweden
Electrovac AG, Klosterneuburg, Austria
Foab Electronic AG, Hisings Backa, Sweden

Fraunhofer Insititut IZM, Berlin Germany
IBM Zurich Research Laboratory, Rüschlikon, Switzerland
Institut d’Electronique de Microtechnologies et de Nanotechnologie, Lille, France
MicReD Ltd. Budapest, Hungary
Robert Bosch GmbH, Stuttgart, Germany
Thales Avionics, Paris, France
VTT Micro and Nanoelectronics, Espoo, Finland   

 

 
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Project co-funded by the European Commission under the "Information and Communication Technologies" Seventh Framework Programme (2007-2013)
 
Contact: Dr. Afshin Ziaei, NANOPACK Coordinator, afshin.ziaei@thalesgroup.com